1. Field of the Invention
The present invention relates to an electrically alterable nonvolatile latch element which can be used as a basic element in the construction of electrically reconfigurable logic blocks.
2. Description of the Prior Art
Electrically erasable and programmable read only memory devices and their different manifestations are now being designed into new applications beyond the traditional domain of nonvolatile memories. Programmable logic arrays which until recently were offered only in fusible link technology are now being offered in nonvolatile memory technologies.
One disadvantage of fusible link technology is that it requires substantial chip area to fabricate the fusible link elements. Also, the programming circuitry required to "blow" the fusible link needs to be large because the link requires a relatively large amount of current to flow through it to "blow" with a certain degree of reliability.
Another technique, known as the laser link technique, utilizes a highly directed laser beam to selectively separate the links in a memory circuit with redundant rows or columns. This technique allows the replacement of a limited number of defective memory locations with the redundant memory locations.
A disadvantage of this technique is that it requires substantial investment in capital equipment to implement.
Another major drawback of the two above-mentioned approaches is that their usefulness is limited by the fact that they are only pre-packaging reconfigurable, i.e. they are not in-circuit programmable.
Integrated circuit devices are now being designed wherein nonvolatile EPROM elements are replacing the fusible links, as in the case of programmable logic arrays and the above-mentioned redundancy circuits. This approach solves the problem of pre-packaging reconfiguration, but it still suffers from high current and voltage requirements. It also requires the use of an external power supply for programming operations and UV light for erasing one prototype configuration before the device can be reconfigured. Thus, the flexibility of in-circuit programming is not available with the EPROM approach.
Several other types of nonvolatile memory elements are disclosed in U.S. Pat. Nos. 4,328,565; 4,409,723; 4,486,769; 4,599,706. However, these memory elements are primarily designed for high cell count memories and are not self-sufficient in that they require relatively complex sense amplifiers and have relatively poor noise immunity.
Additionally, nonvolatile latch circuits have been proposed in U.S. Pat. Nos. 4,132,904 (Harari) and 4,571,704 (Bohac).
U.S. Pat. No. 4,132,904 discloses a volatile/nonvolatile logic latch circuit with a pair of circuit branches, each comprising a field effect transistor and a floating gate field effect transistor connected in series. The control gates of the floating gate field effect transistors are cross-coupled to the common junctions of the series-connected transistors in the other branch. This circuit can be programmed to assume the desired state when power is turned on and can also be intentionally written over if complementary data is to be stored.
U.S. Pat. No. 4,571,704 discloses a nonvolatile latch circuit which assumes the proper state when power is applied to the circuit, irrespective of the power applying conditions. This is accomplished by configuring a pair of circuit branches with each branch comprising a field effect transistor connected in series with a floating gate field effect transistor. The gates of the normal field effect transistors are cross-coupled to the common junctions between the series transistors in the other circuit branch. Also, the control gates of the floating gate field effect transistors are capacitively cross-coupled to the floating gates of the transistors in the other branch.
In the latch proposed by Bohac, if both the nonvolatile memory transistors in the two circuit branches are off (which is normally the case for enhancement floating gate MOSFETs when a device first comes out of wafer fabrication), then when power is turned on, the outputs of the nonvolatile latch are indeterminate since no pull-down to VSS is available until after the memory elements have been programmed.